Electronics Questions Set 3 Competitive Exams

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  1. When will you use a latch and a flipflop in a sequential design?
  2. Design a 1-bit fulladder using a decoder and 2 β€œor” gates?
  3. You have a circuit operating at 20 MHz and 5 volt supply. What would you do to reduce the power consumption in the circuit-reduce the operating frequency of 20Mhz or reduce the power supply of 5Volts and why?
  4. In a nmos transistor, how does the current flows from drain to source in saturation region when the channel is pinched off?
  5. In a SRAM circuit, how do you design the precharge and how do you size it?
  6. In a PLL, what elements (like XOR gates or Flipflops) can be used to design the phase detector?
  7. While synthesis of a design using synopsys design compiler, why do you specify input and output delays?
  8. What difference do you see in the timing reports for a propogated clock and an ideal clock?
  9. What is timeborrowing related to Static timing anaylsis in Primetime?

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